Semiconductor devices such as field effect transistors are common in the electronics industry. Such devices may be formed with extremely small dimensions, such that thousands or even millions of these devices may be formed on a single-crystal silicon substrate or “chip” and interconnected to perform useful functions in an integrated circuit such as a microprocessor.
Although transistor design and fabrication is a highly complex undertaking, the general structure and operation of a transistor are fairly simple. With reference to FIG. 1, a simplified field effect transistor is shown in cross-section. In a field effect transistor a portion of the substrate 100 near the surface is designated as the channel 120 during processing. Channel 120 is electrically connected to source 140 and drain 160, such that when a voltage difference exists between source 140 and drain 160, current will tend to flow through channel 120. The semiconducting characteristics of channel 120 are altered such that its resistivity may be controlled by the voltage applied to gate 190, a conductive layer overlying channel 120. Thus by changing the voltage on gate 190, more or less current can be made to flow through channel 120. Gate 190 and channel 120 are separated by gate dielectric 180; the gate dielectric is insulating, such that between gate 190 and channel 120 little or no current flows during operation (although “tunneling” current is observed with thin dielectrics). However, the gate dielectric allows the gate voltage to induce an electric field in channel 120, giving rise to the name “field effect transistor.”
Generally, integrated circuit performance and density may be enhanced by “scaling”, that is by decreasing the size of the individual semiconductor devices on a chip. Unfortunately, field effect semiconductor devices produce an output signal that is proportional to the width of the channel, such that scaling reduces their output. This effect has generally been compensated for by decreasing the thickness of gate dielectric 180, thus bringing the gate in closer proximity to the channel and enhancing the field effect.
As devices have scaled to smaller and smaller dimensions, the gate dielectric thickness has continued to shrink. Although further scaling of devices is still possible, scaling of the gate dielectric thickness has almost reached its practical limit with the conventional gate dielectric material, silicon dioxide. Further scaling of silicon dioxide gate dielectric thickness will involve a host of problems: extremely thin layers allow for large leakage currents due to direct tunneling through the oxide; because such layers are formed literally from a few layers of atoms, exacting process control is required to repeatably produce such layers; uniformity of coverage is also critical because device parameters may change dramatically based on the presence or absence of even a single monolayer of dielectric material; and finally, such thin layers form poor diffusion barriers to impurities.
Realizing the limitations of silicon dioxide, researchers have searched for alternative dielectric materials which can be formed in a thicker layer than silicon dioxide and yet still produce the same field effect performance. This performance is often expressed as “equivalent oxide thickness”: although the alternative material layer may be thick, it has the equivalent effect of a much thinner layer of silicon dioxide (commonly called simply “oxide”). Many, if not most, of the attractive alternatives for achieving low equivalent oxide thicknesses are metal oxides, such as tantalum pentoxide and barium strontium titanate.
Researchers have found formation of such metal oxides as gate dielectrics to be problematic. At typical metal oxide deposition temperatures, the oxygen ambient or oxygen-containing precursor required to form them tends to also oxidize the silicon substrate, producing an oxide layer at the interface between the substrate and the gate dielectric. The presence of this interfacial oxide layer increases the effective oxide thickness, reducing the effectiveness of the alternative gate dielectric approach. The existence of the interfacial oxide layer places an ultimate constraint on the performance of an alternative dielectric field effect device.